1. Field of the Invention
The present invention relates to changing a pipeline structure of an electronic system, and more particularly, changing a number of pipeline stages in a pipeline structure of an electronic system.
2. Description of the Prior Art
As today's applications for electronic systems grow at ever-increasing rates, the demand for more efficient microprocessor performance is never ceasing. One design for improving the performance in a processor is the use of instruction pipelining. FIG. 9 shows a typical instruction pipeline for a central processing unit (CPU) according to the related art. Processors with pipelining are organized inside into stages, where each stage is organized and linked serially so that in one clock cycle, the logic in each pipeline stage is evaluated and ready to move to the next pipeline stage at the next clock cycle. For example, a generic 4-stage pipeline such as the pipeline 900 shown in FIG. 9 comprises four stages: fetch, decode, execute, and write-back. Almost every microprocessor manufactured today uses at least 2 stages of pipeline, and many designs include pipelines as long as 7, 10, and even 31 stages. This organization of the processor allows overall processing time to be significantly reduced, thus effectively increasing the performance of a processor.
Performance of a processor is measured by its ability to process computer instructions per unit of time. For any processor, the time needed (and thus a measurable performance indicator) to execute a given instruction set for a task can be analyzed as follows:
      time    ⁢                  ⁢          (      s      )        =            icount              freq        *                  icount          /          ccount                      ≈          1              frequency        *        IPC            
where icount is the total instruction count of the task (fixed for the task at hand), ccount is the total cycle count of the task (which is fixed for the processor), and IPC (instructions per cycle) is the average number of instructions that the given processor can execute per clock cycle. For a pipelined processor, a shorter pipeline leads to a higher IPC due to the adverse effects of pipeline bubbling and branching. While running on a same task at the same frequency, a processor with higher IPC leads to higher performance. In other words, a processor with higher IPC value can run at lower frequency to keep the same performance.
According to related art, processors manufactured today are designed with fixed pipeline structures suited to a general “best case” for the processor's intended purpose. Once a number of pipeline stages has been implemented into the pipeline structure design of the processor, the manufactured processors can lower power consumption only by changing the frequency and voltage as needed. The processor is thus subject to a tradeoff between power and performance: power consumption is directly proportional to processor's clock speed, so if the clock speed is reduced, the performance is proportionally decreased. The problem with current processors is that these parameters (changing the frequency or the voltage) cannot meet an optimum trade-off between high performance and low power consumption based on application requirements.